1. Field of the Invention
The present invention relates to a method of evaluating a semiconductor wafer (hereinafter referred to as a wafer). More specifically, the present invention relates to a method of evaluating a semiconductor wafer which can provide an index as to whether generation of a slip line is likely or not. Further, the present invention relates to a method of thermally processing the semiconductor wafer while preventing generation of a slip line, based on the data obtained by the method of evaluation. The present invention also relates to an apparatus for thermally processing the semiconductor wafer improved to prevent generation of the slip line, based on the data obtained by the method of evaluation.
2. Description of the Background Art
FIG. 1 shows steps of manufacturing a general semiconductor device. The manufacturing process of a semiconductor device includes the steps of preparing a wafer, forming an active layer on the wafer, and fabricating a device. In order to form the active layer, thermal processing, which is epitaxial growth (600-700.degree. C.) or activation annealing (up to 800.degree. C.) after ion implantation, are performed. The step of fabricating the device includes the steps of photolithography, forming electrodes and etching.
Now, in the aforementioned thermal processing, it is recognized that the wafer is subjected to plastic deformation and, as a result of plastic deformation, slip lines are generated on the surface of the wafer. A slip line is considered a step such as shown in FIG. 2. Such a slip line decreases production yield of the devices, presenting a significant problem.
To this date, there has never been an index as to whether generation of a slip line (hereinafter simply referred to as a slip) is likely or not in a wafer. Whether a slip is generated or not, that is, resistance to slip formation of a wafer is determined qualitatively by actually performing epitaxial growth, activation annealing and so on in individual thermal processing furnace. The slip resistance could have been found qualitatively for each thermal processing furnace. However, conditions of thermal processing differ from one furnace to another. Accordingly, it has been frequently experienced that slips are generated in a certain thermal processing furnace but not generated in another.
In other words, it has been impossible to determine slip resistance of wafers consistently and quantitatively, and the slip resistance cannot be known until the wafer is actually thermally processed.
As to residual stress of a wafer, residual strain (the strain multiplied by an appropriate elastic constant is the stress) has been evaluated by a photo-elastic method. However, by this method, only an absolute value of the magnitude of the residual strain could be found, and the direction of the residual strain (that is, the direction of the residual stress) could not be determined.
As already described, a slip is considered a macroscopic step generated by formation of a slide which is caused by a dislocation generation and multiplication in the wafer when the stress during thermal processing exceeds the yield stress of the wafer. This may be the case in a wafer without dislocation such as a silicon (Si) wafer. The concept is basically the same in a wafer having dislocations such as Gallium Arsenide (GaAs). However, it is not known whether the dislocation which causes a slide for the first time is newly generated by the stress or an already existing dislocation that slides.
The stress during thermal processing includes thermal stress caused by temperature difference in the plane of the wafer, and dead weight stress caused by the weight of the wafer itself. More specifically, a slip may be generated when a composite stress of thermal stress and dead weight stress exceeds the yield stress of the wafer. Therefore, this yield stress may be used as an index representing slip resistance. In the following, this will be referred to as critical stress for slip defect generation.
The critical stress for slip defect generation can be found by changing the stress applied to the wafer during the process, comparing the presence or absence of actual slips and then finding the critical stress applied when the slip is generated. However, in an actual thermal processing apparatus, it has been impossible to control and change the stress applied to the wafer, and calculation of the applied stress itself has been difficult.
Generation of slips can be significantly reduced when temperature during thermal processing of the wafer is increased or decreased slowly. The reason for this is that thermal stress significantly increases during increase or decrease of temperature (temperature difference in a wafer increases), and the temperature difference in a wafer becomes smaller when the temperature is increased or decreased slowly. However, in order to increase throughput of the wafers, the speed of increasing and decreasing temperature should be as fast as possible while preventing generation of the slips.